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Pdlloyd add verilog syntax #1961

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@pdlloyd pdlloyd commented Aug 10, 2022

IMPORTANT: Please do not create a Pull Request adding a new feature without discussing it first.

The place to discuss new features is the forum: https://zola.discourse.group/
If you want to add a new feature, please open a thread there first in the feature requests section.

Sanity check:

  • Have you checked to ensure there aren't other open Pull Requests for the same update/change?

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(Delete or ignore this section for documentation changes)

  • Are you doing the PR on the next branch?

If the change is a new feature or adding to/changing an existing one:

  • Have you created/updated the relevant documentation page(s)?

Description

This pull request adds syntax highlighting support for SystemVerilog and Verilog. It adds https://github.com/TheClams/SystemVerilog as a submodule. Credit goes to the maintainers of this repository for the syntax files.

I saw here that additional syntaxes will be postponed for a while, and so I will add this syntax manually to my projects until then.

@Keats
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Keats commented Aug 10, 2022

Thanks for the PR. I'm putting any changes to the syntax highlighting on hold though until #1787 has seen some progress to know whether it's viable

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