{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":62921106,"defaultBranch":"master","name":"riscv-linux","ownerLogin":"sifive","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2016-07-08T22:31:43.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/14154771?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1726762482.0","currentOid":""},"activityList":{"items":[{"before":"3e7e531d225d24c20f6e7a8bf0997d3c8b43efe2","after":"134c7025433847fe64ee40b8a1dc5f20dc755896","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-09-20T07:24:07.000Z","pushType":"pr_merge","commitsCount":28,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro\n\n- Revert \"MAX_BLOCK_SIZE\" to original value\n\nSigned-off-by: Xiang Xu \nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro"}},{"before":"94c2d3ef2929409aa23fc53f50397d4e2984594a","after":"d5c6b51b5b654f4889e6ab5ff93ba758991a0450","ref":"refs/heads/dev/kernel/hfp/img-gpu","pushedAt":"2024-09-20T07:22:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro\n\n- Revert \"MAX_BLOCK_SIZE\" to original value\n\nSigned-off-by: Xiang Xu \nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro"}},{"before":"3e7e531d225d24c20f6e7a8bf0997d3c8b43efe2","after":"94c2d3ef2929409aa23fc53f50397d4e2984594a","ref":"refs/heads/dev/kernel/hfp/img-gpu","pushedAt":"2024-09-19T17:16:45.000Z","pushType":"push","commitsCount":29,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro\n\n- Revert \"MAX_BLOCK_SIZE\" to original value\n\nSigned-off-by: Xiang Xu \nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"driver: dw-axi-dmac: Revert MAX_BLOCK_SIZE macro"}},{"before":null,"after":"3e7e531d225d24c20f6e7a8bf0997d3c8b43efe2","ref":"refs/heads/dev/kernel/hfp/img-gpu","pushedAt":"2024-09-19T16:14:42.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: defconfig: hifive-premier-p550: Enable new configs\n\nEnabled kernel debug configs\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: defconfig: hifive-premier-p550: Enable new configs"}},{"before":"edceb098fd2f73cbb1c4de38cccfb89d5e36fd33","after":"3e7e531d225d24c20f6e7a8bf0997d3c8b43efe2","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-09-12T13:14:06.000Z","pushType":"push","commitsCount":5,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: defconfig: hifive-premier-p550: Enable new configs\n\nEnabled kernel debug configs\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: defconfig: hifive-premier-p550: Enable new configs"}},{"before":"5d4ebc36fea5c28cadd5e59f5543c1cd856c7b13","after":"edceb098fd2f73cbb1c4de38cccfb89d5e36fd33","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-09-12T07:13:40.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"DarshanEI","name":null,"path":"/DarshanEI","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/20956574?s=80&v=4"},"commit":{"message":"riscv: dts: hifive-premier-p550: Remove memory nodes\n\nMemory size will be passed through kernel command line based on\nthe RAM detected by U-Boot\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: dts: hifive-premier-p550: Remove memory nodes"}},{"before":"4d981f420bb85b26e927e2a26b834a0ee313f5c1","after":"5d4ebc36fea5c28cadd5e59f5543c1cd856c7b13","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-29T12:47:10.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: dts: hifive-premier-p550: Remove memory nodes\n\nMemory size will be passed through kernel command line based on\nthe RAM detected by U-Boot\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: dts: hifive-premier-p550: Remove memory nodes"}},{"before":"081fb3f3f593861cbb98ece130b45f7a90140b10","after":"4d981f420bb85b26e927e2a26b834a0ee313f5c1","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-29T12:46:17.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: dts: hifive-premier-p550: Remove memory nodes\n\nMemory size will be passed through kernel command line based on\nthe RAM detected by U-Boot\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: dts: hifive-premier-p550: Remove memory nodes"}},{"before":null,"after":"3bc19883c94b2dcfff8746d59c1c27d66b173f9b","ref":"refs/heads/hfp_gfx_integration","pushedAt":"2024-08-27T05:51:39.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"jlakhaniS5","name":"Jeegar Lakhani","path":"/jlakhaniS5","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/98052708?s=80&v=4"},"commit":{"message":"Use .NOTINTERMEDIATE or .SECONDARY based on make version","shortMessageHtmlLink":"Use .NOTINTERMEDIATE or .SECONDARY based on make version"}},{"before":"86da759e8232bd587b031b519a6f774d86600e3c","after":"081fb3f3f593861cbb98ece130b45f7a90140b10","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-23T08:06:05.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: defconfig: hifive-premier-p550: Update command line\n\nUpdated kernel command line\n - Removed stale command lines\n - Moved serial console configs to extlinux conf file\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: defconfig: hifive-premier-p550: Update command line"}},{"before":"29ac17434e527396c06a82888f837c031f749e7e","after":"86da759e8232bd587b031b519a6f774d86600e3c","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-23T05:20:56.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"riscv: defconfig: hifive-premier-p550: Update command line\n\nUpdated kernel command line\n - Removed stale command lines\n - Moved serial console configs to extlinux conf file\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"riscv: defconfig: hifive-premier-p550: Update command line"}},{"before":"b30f63d3fbe0c92384779b736c60822760b1c5d8","after":"29ac17434e527396c06a82888f837c031f749e7e","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-13T16:20:05.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"hifive-premier-p550: Remove 1.5GHz to 1.8GHz cpu freq\n\nRemoved 1.5GHz to 1.8GHz cpu freq from opp-table as the max\nsupported freq for CPU is 1.4GHz\n\nSigned-off-by: Pinkesh Vaghela ","shortMessageHtmlLink":"hifive-premier-p550: Remove 1.5GHz to 1.8GHz cpu freq"}},{"before":"06736c00195027578977359188b53b2f41d0be80","after":"b30f63d3fbe0c92384779b736c60822760b1c5d8","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-13T15:28:58.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"hifive-premier-p550: add defconfig\n\nSigned-off-by: Pritesh Patel ","shortMessageHtmlLink":"hifive-premier-p550: add defconfig"}},{"before":"06736c00195027578977359188b53b2f41d0be80","after":null,"ref":"refs/heads/dev/kernel/v6.6.21-hifive-premier-p550","pushedAt":"2024-08-13T07:16:38.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"}},{"before":null,"after":"06736c00195027578977359188b53b2f41d0be80","ref":"refs/heads/dev/kernel/hifive-premier-p550","pushedAt":"2024-08-13T07:16:37.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"tty/serial: Add RISC-V SBI debug console based earlycon\n\nWe extend the existing RISC-V SBI earlycon support to use the new\nRISC-V SBI debug console extension.\n\nSigned-off-by: Anup Patel \nReviewed-by: Andrew Jones \nAcked-by: Greg Kroah-Hartman \nLink: https://lore.kernel.org/r/20231124070905.1043092-4-apatel@ventanamicro.com\nSigned-off-by: Palmer Dabbelt ","shortMessageHtmlLink":"tty/serial: Add RISC-V SBI debug console based earlycon"}},{"before":null,"after":"4253dfba9f1a7df824902e76dbfadd51c638052a","ref":"refs/heads/cfi_spec_split_march24_v6.8-rc7/fixes","pushedAt":"2024-08-09T05:32:37.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"arch/riscv: workaround of user mode cfi for vdso\n\nAdd landing pad instruction to vdso function as a workaround to support\nuser mode cfi.\n\nSigned-off-by: Jim Shu ","shortMessageHtmlLink":"arch/riscv: workaround of user mode cfi for vdso"}},{"before":"3c682634bb78c8f60dd3bf01ff065573d103fe1c","after":"06736c00195027578977359188b53b2f41d0be80","ref":"refs/heads/dev/kernel/v6.6.21-hifive-premier-p550","pushedAt":"2024-08-07T11:18:40.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"tty/serial: Add RISC-V SBI debug console based earlycon\n\nWe extend the existing RISC-V SBI earlycon support to use the new\nRISC-V SBI debug console extension.\n\nSigned-off-by: Anup Patel \nReviewed-by: Andrew Jones \nAcked-by: Greg Kroah-Hartman \nLink: https://lore.kernel.org/r/20231124070905.1043092-4-apatel@ventanamicro.com\nSigned-off-by: Palmer Dabbelt ","shortMessageHtmlLink":"tty/serial: Add RISC-V SBI debug console based earlycon"}},{"before":null,"after":"3c682634bb78c8f60dd3bf01ff065573d103fe1c","ref":"refs/heads/dev/kernel/v6.6.21-hifive-premier-p550","pushedAt":"2024-08-06T07:19:31.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Pritesh201192","name":null,"path":"/Pritesh201192","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/139881210?s=80&v=4"},"commit":{"message":"ttm: disallow cached mapping\n\nSigned-off-by: Icenowy Zheng ","shortMessageHtmlLink":"ttm: disallow cached mapping"}},{"before":"a97eb5d6ed5ce0c8786c49b02013ed3acbe88d23","after":"553f1b3e3010561dfdf62780c91bfe1954d07caa","ref":"refs/heads/dev/andyc/dyn-ftrace-v4","pushedAt":"2024-05-23T08:25:16.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: ftrace: support fastcc in Clang for WITH_ARGS\n\n- [1]: https://reviews.llvm.org/D68559\nSigned-off-by: Andy Chiu ","shortMessageHtmlLink":"riscv: ftrace: support fastcc in Clang for WITH_ARGS"}},{"before":null,"after":"a97eb5d6ed5ce0c8786c49b02013ed3acbe88d23","ref":"refs/heads/dev/andyc/dyn-ftrace-v4","pushedAt":"2024-05-23T07:58:45.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: ftrace: support fastcc in Clang for WITH_ARGS\n\n- [1]: https://reviews.llvm.org/D68559\nSigned-off-by: Andy Chiu ","shortMessageHtmlLink":"riscv: ftrace: support fastcc in Clang for WITH_ARGS"}},{"before":"d993a079fbad32708d89e8269b128d3011ebb847","after":"c57ca652fbf32ab10c1d69fe50c7bb58ab735f36","ref":"refs/heads/dev/for-next/kernel-mode-vector-v11","pushedAt":"2024-01-15T05:16:17.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: lib: add vectorized mem* routines\n\ntest\n\nProvide vectorized memcpy/memset/memmove to accelerate common memory\noperations. Also, group them into V_OPT_TEMPLATE3 macro because their\nsetup/tear-down and fallback logics are the same.\n\nThe optimal size for the kernel to preference Vector over scalar,\nriscv_v_mem*_threshold, is only a heuristic for now. We can add DT\nparsing if people feel the need of customizing it.\n\nThe original implementation of Vector operations comes from\nhttps://github.com/sifive/sifive-libc, which we agree to contribute to\nLinux kernel.\n\nSigned-off-by: Andy Chiu \n---\nChangelog v7:\n - add __NO_FORTIFY to prevent conflicting function declaration with\n macro for mem* functions.\nChangelog v6:\n - provide kconfig to set threshold for vectorized functions (Charlie)\n - rename *thres to *threshold (Charlie)\nChangelog v4:\n - new patch since v4","shortMessageHtmlLink":"riscv: lib: add vectorized mem* routines"}},{"before":null,"after":"d993a079fbad32708d89e8269b128d3011ebb847","ref":"refs/heads/dev/for-next/kernel-mode-vector-v11","pushedAt":"2024-01-13T12:58:10.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: lib: add vectorized mem* routines\n\ntest\n\nProvide vectorized memcpy/memset/memmove to accelerate common memory\noperations. Also, group them into V_OPT_TEMPLATE3 macro because their\nsetup/tear-down and fallback logics are the same.\n\nThe optimal size for the kernel to preference Vector over scalar,\nriscv_v_mem*_threshold, is only a heuristic for now. We can add DT\nparsing if people feel the need of customizing it.\n\nThe original implementation of Vector operations comes from\nhttps://github.com/sifive/sifive-libc, which we agree to contribute to\nLinux kernel.\n\nSigned-off-by: Andy Chiu \n---\nChangelog v7:\n - add __NO_FORTIFY to prevent conflicting function declaration with\n macro for mem* functions.\nChangelog v6:\n - provide kconfig to set threshold for vectorized functions (Charlie)\n - rename *thres to *threshold (Charlie)\nChangelog v4:\n - new patch since v4","shortMessageHtmlLink":"riscv: lib: add vectorized mem* routines"}},{"before":null,"after":"9a232396318f387a86315b3d708e8a4f8a17cbb0","ref":"refs/heads/riscv/for-next/vector-v20","pushedAt":"2023-05-18T15:40:09.622Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"selftests: add .gitignore file for RISC-V hwprobe\n\nThe executable file \"hwprobe\" should be ignored by git, adding it to fix\nthat.\n\nSigned-off-by: Andy Chiu ","shortMessageHtmlLink":"selftests: add .gitignore file for RISC-V hwprobe"}},{"before":null,"after":"d57cb462e6851119a6cfdd6a16e15118d3f63974","ref":"refs/heads/riscv/for-next/vector-v19","pushedAt":"2023-05-09T09:32:42.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: Add documentation for Vector\n\nThis patch add a brief documentation of the userspace interface in\nregard to the RISC-V Vector extension.\n\nSigned-off-by: Andy Chiu \nReviewed-by: Greentime Hu \nReviewed-by: Vincent Chen ","shortMessageHtmlLink":"riscv: Add documentation for Vector"}},{"before":null,"after":"92d32b7c45b290acb3df7aa82076e243ff19876f","ref":"refs/heads/riscv/for-next/vector-v18","pushedAt":"2023-04-14T15:55:07.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: Enable Vector code to be built\n\nThis patch adds a config which enables vector feature from the kernel\nspace.\n\nSigned-off-by: Guo Ren \nCo-developed-by: Greentime Hu \nSigned-off-by: Greentime Hu \nSuggested-by: Vineet Gupta \nSuggested-by: Atish Patra \nCo-developed-by: Andy Chiu \nSigned-off-by: Andy Chiu \nReviewed-by: Conor Dooley \nReviewed-by: Heiko Stuebner \nTested-by: Heiko Stuebner ","shortMessageHtmlLink":"riscv: Enable Vector code to be built"}},{"before":null,"after":"9516c826c9369f9c08d9054929ec8ddd2d4c6732","ref":"refs/heads/riscv/for-next/vector-v17","pushedAt":"2023-03-27T16:33:30.284Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"riscv: Enable Vector code to be built\n\nThis patch adds a config which enables vector feature from the kernel\nspace.\n\nSigned-off-by: Guo Ren \nCo-developed-by: Greentime Hu \nSigned-off-by: Greentime Hu \nSuggested-by: Vineet Gupta \nSuggested-by: Atish Patra \nCo-developed-by: Andy Chiu \nSigned-off-by: Andy Chiu \nReviewed-by: Conor Dooley ","shortMessageHtmlLink":"riscv: Enable Vector code to be built"}},{"before":null,"after":"ca2e1b2fa5dccfcce4a2640defed01d30501b832","ref":"refs/heads/riscv/for-next/vector-v16","pushedAt":"2023-03-23T14:35:12.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask optimizations\"","shortMessageHtmlLink":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask …"}},{"before":"d81661cc85179991685652e1e39cebb7c5b5910f","after":"49cb05eaacd45392d4ffeaf71bcc548c43f0f298","ref":"refs/heads/riscv/for-next/vector-v15","pushedAt":"2023-03-17T11:14:31.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask optimizations\"","shortMessageHtmlLink":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask …"}},{"before":null,"after":"d81661cc85179991685652e1e39cebb7c5b5910f","ref":"refs/heads/riscv/for-next/vector-v15","pushedAt":"2023-03-17T10:53:55.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"AndybnACT","name":"Andy Chiu","path":"/AndybnACT","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/26669276?s=80&v=4"},"commit":{"message":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask optimizations\"","shortMessageHtmlLink":"internal: fix \"596ff4a: cpumask: re-introduce constant-sized cpumask …"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEu6nf_QA","startCursor":null,"endCursor":null}},"title":"Activity · sifive/riscv-linux"}